1. Field of the Invention
The present invention relates to a synchronous clock generation circuit.
2. Description of the Background Art
In a conventional semiconductor integrated circuit, a phase-locked loop (PLL) circuit has been used in order to achieve synchronization of phases of clocks in and out of a chip, or to obtain a clock having a frequency being a multiple of that of an external clock. The PLL circuit is broadly categorized into an analog PLL circuit and a digital PLL circuit.
In general, the analog PLL circuit is constituted of an analog phase comparator, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider.
On the other hand, the digital PLL circuit is generally constituted of a digital phase comparator, a control circuit, a digital controlled oscillator, and a frequency divider.
In a current PLL circuit, whereas the analog phase comparator used in the analog PLL circuit attains an excellent phase noise characteristic, it has a narrow capture range. On the other hand, though the digital phase comparator used in the digital PLL circuit attains a wide capture range, its phase noise characteristic is poorer than that of the analog phase comparator. Therefore, Japanese Patent Laying-Open No. 2002-152039 discloses a PLL circuit utilizing combined advantages of the both.
In the conventional art disclosed in Japanese Patent Laying-Open No. 2002-152039, in order to achieve the low noise characteristic of the analog phase comparator and the wide lock capture characteristic of the digital phase comparator, two types of phase comparators are switched before and after locking. On the other hand, as a conventional VCO is employed, problems originating from the VCO still remain.
First, a VCO used in the analog PLL circuit will be described. A general ring oscillator-type VCO is constituted of an odd number of inversion delay stages connected so as to form a ring. An oscillation frequency is varied when a delay time at each delay stage varies in accordance with a control voltage. The analog PLL circuit using such a VCO disadvantageously has a narrow capture range.
For example, the VCO attains a high oscillation frequency when the control voltage is raised, while it attains a low oscillation frequency when the control voltage is lowered. In general, a control voltage of a value between a ground voltage and a power supply potential is applied. The control voltage actually applicable, however, is of a value in a range from (a threshold voltage of an N-channel transistor) to (a potential obtained by subtracting a threshold voltage of a P-channel MOS transistor and the like from the power supply potential), that is, in a range from Vthn to VDD−|Vthp|.
As the tendency toward lower voltage grows, a proportion of the threshold voltage with respect to the power supply voltage will be relatively larger. Therefore, a range available for use as the control voltage tends to be narrower. In order to obtain a similar oscillation frequency range (a range from a lowest frequency to a highest frequency) in a narrower control voltage range, sensitivity of the VCO may be enhanced, however, this will lead to increased susceptibility to noise.
FIG. 15 illustrates a range available for use in the VCO.
As shown in FIG. 15, considering a change due to a process, a power supply voltage and a temperature, the oscillation frequency range under respective conditions in states from best to worst varies to a large extent.
Here, solely a range where all oscillation frequency ranges overlap, that is, the range available for use indicated in FIG. 15, is applicable as the oscillation frequency range of the VCO. As the tendency toward smaller size and lower voltage grows, influence from a change in the process or the power supply voltage will be more significant, and ensuring the oscillation frequency range will increasingly be difficult. Generally, as a lock-in range of the analog PLL circuit is substantially equal to the oscillation frequency range of the VCO, maintaining a wide oscillation frequency range of the VCO is a major future challenge.
The digital controlled oscillator used in the digital PLL circuit will now be described. The digital controlled oscillator is constituted of a logic inversion circuit (inverter), a plurality of delay stages, and a selection circuit selecting any one of outputs from the plurality of delay stages and providing the selected output to an input of the logic inversion circuit. When the delay stage selected by the selection circuit is changed, the number of delay stages and inverter connected so as to form a loop is varied, whereby the total delay time is changed. The oscillation frequency can thus be varied.
In other words, in the digital controlled oscillator used in the digital PLL circuit, the oscillation frequency is controlled by changing the number of delay stages. Accordingly, if the delay time of one delay stage is shortened and the number of delay stages is increased, a wider lock-in range can readily be achieved. On the other hand, the digital controlled oscillator used in the digital PLL tends to generate jitter not smaller than that caused by at least one delay stage in nature. This jitter is relatively larger than that in the VCO used in the analog PLL circuit, and a jitter characteristic is not necessarily excellent.
As described above, in the current PLL circuit, it has been difficult to ensure the lock-in range in the analog PLL circuit, while the jitter characteristic of the digital PLL circuit has been poor due to characteristics of an oscillator used.